module flash_led_top(
  input clk,
  input rst_n,
  output [3:0] led
);
reg [3:0] led;
reg [25:0] pre_cnt;

wire sys_clk;

    GW_PLL ul(
        .clkout(sys_clk), //output clkout
        .clkin(clk) //input clkin
    );

always@(posedge sys_clk or negedge rst_n) begin
  if (~rst_n) begin
    pre_cnt<=0;
    led<=0;
  end
  else begin
    pre_cnt<=pre_cnt+1;
    if (pre_cnt==0) begin
      led<=led+1;
    end
  end

end

endmodule


